1. Field of the Invention
The present invention relates to a display device for displaying an image by inputting a digital video signal. In particular, the present invention relates to a display device having light emitting elements. Further, the present invention relates to an electronic equipment that uses the display device.
2. Description of the Related Art
A display device having a light emitting element disposed in each pixel which performs display of an image by controlling light emitted from the light emitting elements is explained below.
The explanation throughout this specification uses elements (OLED elements) having a structure in which an organic compound layer for emitting light when an electric field is generated is sandwiched between an anode and a cathode, for the light emitting elements, but the present invention is not limited to this structure.
Further, the explanation within this specification uses elements that utilize light emitted when making a transition from singlet excitons to a base state (fluorescence), and those that utilize light emitted when making a transition from triplet excitons to a base state (phosphorescence).
Layers such as hole injecting layers, hole transporting layers, light emitting layers, electron transporting layers, electron injecting layers can be given as organic compound layers. Light emitting elements basically are shown by structures in which an anode, a light emitting layer, and a cathode overlap in this order. In addition, structures such as a structure in which an anode, a hole injecting layer, a light emitting layer, an electron injecting layer, and a cathode are overlapped in this order, and one in which an anode, a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, an electron injecting layer, and a cathode are overlapped in this order may also be used.
Note that the organic compound layers are not limited to laminate structures in which layers such as hole injecting layers, hole transporting layers, light emitting layers, electron transporting layers, and electron injecting layers are clearly separated from each other. That is, the organic compound layers may also have a structure having a layer in which the materials used for structuring hole injecting layers, hole transporting layers, light emitting layers, electron transporting layers, and electron injecting layers are mixed.
Further, any types of materials of low molecular weight materials, high molecular weight materials, and intermediate molecular weight materials may be used as the OLED element organic compound layers.
Note that, in this specification, the term intermediate molecular weight material indicates materials having a molecularity equal to or less than 20, or those in which the length of the chained molecules is equal to or less than 10 μm and which do not have sublimation property.
A display devices is structured by a display and peripheral circuits for inputting signals to the display.
The structure of the display is explained below.
The display is structured by a source signal line driver circuit, a gate signal line driver circuit, and a pixel portion. The pixel portion has pixels disposed in a matrix shape.
Thin film transistors (hereafter referred to as TFTs) are arranged in each pixel of the pixel portion. A method of placing two TFTs in each pixel and controlling light emitted from the light emitting element of each pixel is explained.
FIG. 7 shows a structure of a pixel portion of a display device.
Source signal lines S1 to Sx, gate signal lines G1 to Gy, and electric power source supply lines V1 to Vx are arranged in a pixel portion 700, and x columns and y rows (where x and y are natural numbers) of pixels are also placed in the pixel portion. Each pixel 800 has a switching TFT 801, a driver TFT 802, a storage capacitor 803, and a light emitting element 804.
An enlarged view of one pixel of the pixel portion of FIG. 7 is shown in FIG. 8.
The pixel is structured by one source signal line S of the source signal lines S1 to Sx, one gate signal line G of the gate signal lines G1 to Gy, one electric power source supply line V of the electric power source supply lines V1 to Vx, the switching TFT 801, the driver TFT 802, the storage capacitor 803, and the light emitting element 804.
A gate electrode of the switching TFT 801 is connected to the gate signal line G, and one of a source region and a drain region of the switching TFT 801 is connected to the source signal line S, while the other one is connected to a gate electrode of the driver TFT 802 or to one electrode of the storage capacitor 803. One of a source region and a drain region of the driver TFT 802 is connected to the electric power source supply line V, while the other one is connected to an anode or a cathode of the light emitting element 804. The electric power source supply line V is connected to one of the two electrodes of the storage capacitor 803, namely the electrode on the side to which the driver TFT 802 and the switching TFT 801 are not connected.
The anode of the light emitting element 804 is referred to as a pixel electrode, and the cathode of the light emitting element 804 is referred to as an opposing electrode, within this specification for cases in which the source region or the drain region of the driver TFT 802 is connected to the anode of the light emitting element 804. On the other hand, if the source region or the drain region of the driver TFT 802 is connected to the cathode of the light emitting element 804, then the cathode of the light emitting element 804 is referred to as the pixel electrode, and the anode of the light emitting element 804 is referred to as the opposing electrode.
Further, an electric potential imparted to the electric power source supply line V is referred to as an electric power source electric potential, and an electric potential imparted to the opposing electrode is referred to as an opposing electric potential.
The switching TFT 801 and the driver TFT 802 may be either p-channel TFTs or n-channel TFTs. However, it is preferable that the driver TFT 802 be a p-channel TFT, and that the switching TFT 801 be an n-channel TFT for cases in which the pixel electrode of the light emitting element 804 is the anode. Conversely, it is preferable that the driver TFT 802 be an n-channel TFT, and that the switching TFT 801 be a p-channel TFT if the pixel electrode is the cathode.
Note that the storage capacitor 803 need not always be formed.
For example, a parasitic capacitance generally referred to as a gate capacitance is formed in overlapping regions for cases where there is an LDD region in which the n-channel TFT used as the driver TFT 802 is formed so as to overlap with a gate electrode through a gate insulating film. It is possible to actively use this parasitic capacitance as a storage capacitor for storing a voltage applied to the gate electrode of the driver TFT 802.
Operation during display of an image with the aforementioned pixel structure is explained below.
A signal is input to the gate signal line G, and the electric potential of the gate electrode of the switching TFT 801 changes, thereby changing a gate voltage. The signal is input to the gate electrode of the driver TFT 802 by the source signal line S, via the source and drain of the switching TFT 801 which thus has been placed in a conductive state. Further, the signal is stored in the storage capacitor 803. The gate voltage of the driver TFT 802 changes in accordance with the signal input to the gate electrode of the driver TFT 802, thereby placing the source and drain in a conductive state. The electric potential of the electric power source supply line V is imparted to the pixel electrode of the light emitting element 804 through the driver TFT 802. The light emitting element 804 thus emits light.
A method of expressing gray scales with pixels having such a structure is explained.
Gray scale expression methods can be roughly divided into analog methods and digital methods. Digital methods have advantages compared to analog methods, such as being geared to multiple gray scales.
A digital gray scale expression method is focused upon here.
A time gray scale method can be given as the digital gray scale expression method.
A time gray scale driving method is explained in detail below.
The time gray scale driving method is a method of expressing gray scales by controlling the period that each pixel of a display device emits light.
If a period for displaying one image is taken as one frame period, then one frame period is divided into a plurality of subframe periods.
Turn on and turn off, namely whether or not the light emitting element of each pixel is made to emit light or to not emit light, is performed for each subframe period. The period during which the light emitting element emits light in one frame period is controlled, and a gray scale for each pixel is expressed.
The time gray scale driving method is explained in detail using timing charts of FIGS. 5A and 5B.
Note that an example of expressing gray scales using a 4-bit digital image signal is shown in FIG. 5A.
Note also that FIG. 7 and FIG. 8 may be referred to regarding the structure of the pixel portion and the structure of the pixels, respectively.
In accordance with an external electric power source (not shown in the figures), the opposing electric potential can be switched over between an electric potential on the same order as the electric potential of the electric power source supply lines V1 to Vx (electric power source electric potential), and an electric potential of the electric power source supply lines V1 to Vx on an order sufficient to make the light emitting element 804 emit light.
One frame period F is divided into a plurality of subframe periods SF1 to SF4.
The gate signal line G1 is selected first in the first subframe period SF1, and a digital image signal is input from the source signal lines S1 to Sx to each of the pixels having the switching TFTs 801 with gate electrodes connected to the gate signal line G1. The driver TFT 802 of each pixel is placed in an on state or an off state by the input digital image signal.
The term “on state” for a TFT in this specification indicates that the TFT is in a state in which there is conduction between the source and the drain in accordance with a gate voltage. Further, the term “off state” for a TFT indicates that there is a non-conductive state between the source and the drain in accordance with the gate voltage.
The opposing electric potential of the light emitting elements 804 is set nearly equal to the electric potential of the electric power source supply lines V1 to Vx (electric power source electric potential) at this point, and therefore the light emitting elements 804 do not emit light even in pixels having their driver TFT 802 in an on state.
FIG. 5B is a timing chart showing operation when the digital image signal is input to the driver TFT 802 of each pixel.
A sampling period in which a source signal line driver circuit (not shown in the figures) samples signals corresponding to each of the source signal lines are shown by reference symbols S1 to Sx in FIG. 5B. The sampled signals are output at the same time to all of the source signal lines in a return period in the figure. The signals thus output are thus input to the gate electrodes of the driver TFTs 802 in the pixels which have selected gate signal lines.
The aforementioned operations are repeated for all of the gate signal lines G1 to Gy, and a write in period Ta1 is completed.
Note that a period for write-in during the first subframe period SF1 is called Ta1. In general, a write in period of a j-th sub-frame period SFj (where j is a natural number) is called Taj.
The opposing electric potential changes when the write in period Ta1 is complete, so as to have an electric potential difference from the electric power source electric potential on an order so that the light emitting element 804 will emit light. A display period Ts1 thus begins.
Note that the display period of the first subframe period SF1 is called Ts1. In general, a display period of the j-th sub-frame period SFj (where j is a natural number) is denoted by using a reference symbol Tsj.
The light emitting elements 804 of each pixel are placed in a light emitting state or a non-light emitting state, corresponding to the input signal, in the display period Ts1.
As shown in FIG. 5A, the above operations are repeated for all of the subframe periods SF1 to SF4, thereby completing one frame period F1.
The length of the display periods Ts1 to Ts4 of the subframe periods SF1 to SF4 are set appropriately here, and gray scales are expressed by an accumulation of the display periods of the subframe period during which the light emitting elements 804 emit light. In other words, the total amount of the turn on time within one frame period is used to express the gray scales.
A method of generally expressing 2n gray scales by inputting an n-bit digital video signal, is explained.
One frame period is divided into n sub-frame periods SF1 to SFn at this point, for example, and the ratios of the lengths of the display periods Ts1 to Tsn of the sub-frame periods SF1 to SFn are set so as to be Ts1::Ts2:: . . . ::Tsn−1::Tsn=20::2−1:: . . . ::2−n+2::2−n+1. Note that the lengths of the write in periods Ta1 to Tan are all the same.
Within one frame period, the gray scale of the pixels in the frame period is determined by finding the total of the display period Ts during which a light emitting state is selected in the light emitting elements 804. For example, if the brightness for a case in which a pixel emits light during all of the display periods is taken to be 100% when n=8, then a brightness of 1% can be expressed if the pixel emits light in the display period Ts8 and in the display period Ts7. A 60% brightness can be expressed for cases in which the pixel emits light in the display periods Ts6, Ts4, and Ts1.
A circuit for inputting a signal in order to perform the above-stated time gray scale driving method to the source signal line driver circuit and the gate signal line driver circuit of the display is explained using FIG. 10.
Signals input to the display device are referred to as digital video signals within this specification. Note that the example explained here is that of a display device into which an n-bit digital video signal is input.
The display device is structured by: a display 1100 composed of a source signal line driver circuit 1107, a gate signal line driver circuit 1108, and a pixel portion 1109; a signal control circuit 1101; and a display controller 1102.
The digital video signal is read in by the signal control circuit 1101, and the signal control circuit 1101 outputs a digital image signal (VD) to the display 1100.
A signal converted for input to the display 1100 in the signal control circuit, the edited digital video signal, is referred to as the digital image signal within this specification.
Signals for driving the source signal line driver circuit 1107 and the gate signal line driver circuit 1108 of the display 1100 are input from the display controller 1102.
The structure of the signal control circuit 1101 and the structure of the display controller 1102 are explained.
Note that the source signal line driver circuit 1107 of the display 1100 is structured by a shift register 1110, an LAT (A) 1111, and an LAT (B) 1112. In addition, although not shown in the figures, circuits such as level shifters and buffers may also be formed.
The signal control circuit 1101 is structured by a CPU 1104, a memory A 1105, a memory B 1106, and a memory controller 1103.
The digital video signal input to the signal control circuit 1101 is input to the memory A 1105 through the CPU 1104.
In other words, the digital signal for each bit, corresponding to each pixel, in the digital video signal is input to the memory A 1105 and stored.
The memory A 1105 has a capacity that is capable of storing the n-bit digital signal for all pixels of the pixel portion 1109 of the display 1100.
When one frame period portion of the digital signal is stored in the memory A 1105, the digital signal for each bit is read out in order by the memory controller 1103, and then input to the source signal line driver circuit as the digital image signal VD.
The digital video signal corresponding to the next frame period is then input to the memory B 1106, through the CPU 1104, when read out of the digital signals stored in the memory A 1105 begins, and storage of the digital video signal in the memory B begins. Similarly to the memory A 1105, the memory B 1106 also has a capacity that is capable of storing the n-bit digital signal for all pixels of the pixel portion of the display device.
The signal control circuit 1101 thus has the memory A 1105 and the memory B 1106, each of which is capable of storing one frame period portion of the n-bit digital signal. The digital video signal is sampled using the memory A 1105 and the memory B 1106 alternately.
The signal control circuit 1101 for storing signals by using the two memories alternately, namely the memory A 1105 and the memory B 1106, is shown here. In general, however, memories capable of storing information corresponding to a plurality of frame portions are used. These memories can be used alternately.
The structure of the memory controller 1103, used for controlling input of the digital video signal to, and read out of the signals from, the memory A 1105 and the memory B 1106 of the signal control circuit 1101, is explained using FIG. 11.
In FIG. 11, the memory controller 1103 is structured by a memory read/write control (hereafter referred to as memory R/W) circuit 1202, a standard oscillator circuit 1203, a variable frequency divider circuit 1204, an x-counter 1205a, a y-counter 1205b, an x-decoder 1206a, and a y-decoder 1206b. 
Both memories, namely the memory A and the memory B, of the aforementioned signal control circuit are hereafter taken together and denoted as memory. Further, the memory is structured by a plurality of memory elements, and the memory elements are selected by using (x,y) addresses.
Signals from the CPU 1104 are input to the standard oscillator circuit 1203. Signals from the standard oscillator circuit 1203 are input to the variable frequency divider circuit 1204 and converted to signals having an appropriate frequency. The signals from the variable frequency divider circuit 1204 select x addresses of the memory through the x-counter 1205a and the decoder 1206a. At the same time, the signals from the variable frequency divider circuit 1204 select y addresses of the memory through the y-counter 1205b and the y-decoder 1206b. In this way, the addresses of the memory (x, y) are selected. Furthermore, signals from the CPU 1104 are input to the memory R/W circuit 1202, and a memory R/W signal for selecting write in operation of the signal to the memory, or read out operation of the signal from the memory, is output.
Memory addresses for writing in, or reading out, the digital signals are thus selected by the memory x address and the memory y address. Operations for write of the digital signal to, or read out of the digital signal from, the memory element selected by this address are performed in accordance with the memory R/W signal.
Next, the structure of the display controller 1102 in FIG. 10 is explained below.
The display controller 1102 outputs signals such as start pulses (S_SP, G_SP) and clock pulses (S_CLK, G_CLK) to the source signal line driver circuit 1107 and to the gate signal line driver circuit 1108.
The structure of the display controller 1102 is explained using FIG. 12.
The display controller 1102 is structured by a standard clock generator circuit 1301, a horizontal clock generator circuit 1303, a vertical clock generator circuit 1304, and an electric power source control circuit 1305 used for the light emitting elements.
A clock signal 31 input from the CPU 1104 is input to the standard clock generator circuit 1301, and a standard clock is generated. The standard clock is input to the horizontal clock generator circuit 1303 and to the vertical clock generator circuit 1304. Further, a horizontal period signal 32 for determining a horizontal period is input from the CPU 1104 to the horizontal clock generator circuit 1303, and the clock pulse S_CLK and the start pulse S_SP used for the source signal line driver circuit are output. At the same time, a vertical period signal 33 for determining a vertical period is input from the CPU 1104 to the vertical clock generator circuit 1304, and the clock pulse G_CLK and the start pulse G_SP used for the gate signal line driver circuit are output.
FIG. 10 will be referred to again.
The start pulse S_SP and the clock pulse S_CLK output from the display controller 1102 and used for the source signal line driver circuit are input to the shift register 1110 of the source signal line driver circuit 1107 in the display 1100. Further, the start pulse G_SP and the clock pulse G_CLK used for the gate signal line driver circuit are input to the gate signal line driver circuit 1108 of the display 1100.
In the display controller 1102, the electric power source controller circuit 1305 used for the light emitting element maintains the electric potential of the opposing electrode of the light emitting element of each pixel in the display at the same electric potential as the electric power source electric potential during the write in period. Further, the electric power source controller circuit 1305 controls the electric potential of the opposing electrode so that it changes to have an electric potential difference, with respect to the electric power source electric potential, on an order such that the light emitting element emits light.
The display device thus displays an image.
It is preferable that the display device have as little electric power consumption as possible here. Low electric power consumption is especially desirable if the display device is incorporated into a portable information device or the like to be utilized.
A method of suppressing the electric power consumption of the display device by reducing the number of gray scales during image display (the number of gray scales expressed) in the case in which a multiple gray scale display is not required, is proposed.
This method is explained in detail below using a timing chart of FIG. 9.
A display device, into which a 4-bit signal is input to thereby display 24 gray scales, is noticed. Gray scales are expressed by using only the most significant 1-bit signal (digital signal) in accordance with a switching signal. A method of reducing the electric power consumption of the display device is explained here in an example.
A case of inputting a 4-bit digital video signal and expressing 24 gray scales is referred to as a first display mode, and a case of expressing two gray scales by using only the most significant 1-bit signal is referred to as a second display mode.
Note that, in general, in the case of using an n-bit signal as the input digital video signal, the expression of gray scales using the n-bit signal is referred to as the first display mode. The expression of gray scales using only m bits of the signal (where m is a natural number less than n) from among the n bits is referred to as the second display mode.
Note that the first bit of the n-bit digital image signal is taken as the most significant bit, and that the n-bit is taken as the least significant bit.
In the second display mode, gray scales are expressed without using the signal corresponding to the lower bits of the digital image signal in the first display mode.
One frame period is divided into four sub-frame periods SF1 to SF4. The sub-frame periods SF1 to SF4 express in order the sub-frame period corresponding to the most significant bit to the sub-frame period corresponding to the least significant bit, and appear in this order to structure one frame period.
In the first display mode, the gray scales are expressed using all of the input 4-bit digital video signal, and therefore the signal input from the signal controller circuit to the source signal line driver circuit is the same as the case of expressing gray scales using the 4-bit digital image signal. Further, the clock pulse S_CLK and the start pulse S_SP for the source signal line driver circuit and the clock pulse G_CLK and the start pulse G_SP for the gate signal line driver circuit which are output from the display controller, are also the same as those used in the case of expressing gray scales using the 4-bit digital image signal.
A method of driving the display device in the second display mode is explained below.
A timing chart showing the method of driving the display device in the second display mode is shown in FIG. 9.
Signals are input to respective pixels in the first sub-frame period SF1. When the signals are input to all of the pixels, the opposing electric potential changes to have an electric potential difference from the electric power source electric potential so that the light emitting elements emit light. The light emitting elements of all of the pixels are thus placed in a light emitting state or a non-light emitting state.
Operations in the first sub-frame period are the same as the operations performed in the first display mode.
Next, the digital image signal is also similarly written to all of the pixels in the write in period of the second sub-frame period. However, in the following display period, the electric potential of the opposing electrode does not change so as to have an electric potential difference from the electric power source electric potential so that the light emitting element emit light. That is, the light emitting elements of the pixels do not emit light in the display period of the second sub-frame period, regardless of the signals input to the pixels. This period is denoted as non-display.
Operations in the second sub-frame period are similarly repeated in the third sub-frame period and in the fourth sub-frame period to thus complete one frame period.
The period in which the pixels perform display during one frame period is only the first sub-frame period. The number of times that the light emitting elements of the pixels emit light can thus be lowered in the second display mode, and the electric power consumption of the display device can be reduced.
In a conventional display device, each pixel of the display device does not perform display in a period except a sub-frame period which is corresponding to an upper bit in switching to a second display mode for expressing gray scales without using information of lower bits. However, in each driver circuit (source signal line driver circuit and gate signal line driver circuit), write in operation of the digital video signal to each pixel is performed. At this time, start pulses, clock pulses and the like are input to each driver circuit of the display device to thereby continue the operation.
Therefore, even in the second display mode in which gray scale display is performed with a small amount of information, each of the driver circuits repeatedly performs sampling of the digital image signal, which is the same as sampling operations in the first display mode. Electric power is therefore consumed for sampling, and there is a problem that the electric power consumption cannot be made smaller.
Furthermore, in the sub-frame periods except the sub-frame period during which display is actually performed, the pixels are all uniformly in a non-display state during which light is not emitted. There is therefore a problem that the proportion of the effective display period in one frame period is small.